LOGIC SYNTHESIS FOR LOW POWER Luca Benini DEIS -
نویسندگان
چکیده
Energy-e cient design of integrated circuits requires specialized tools and technologies. This chapter surveys some of the most important contributions in logic synthesis for achieving low-power consumption, by means of gate-level and register-transfer level restructuring. It presents also specialized techniques that leverage speci c low-power silicon tech-
منابع مشابه
Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chip
Embedded systems designers are turning to multicore architectures to satisfy the ever-growing computational needs of applications within a reasonable power envelope. One of the most daunting challenges for MultiProcessor System-on-Chip (MPSoC) platforms is the development of tools for efficient mapping multi-task applications onto hardware platforms. Software mapping can be formulated as an opt...
متن کاملOptimal synthesis of gated clocks for low-power Finite-State Machines
The automatic synthesis of low power FSMs with gated clocks relies on e cient algorithms for the synthesis and optimization of dedicated clock-stopping circuitry. In a previous paper [3] we have described a framework for the transformation of FSMs and the extraction of input and state conditions where the clock can be safely stopped without modifying the external behavior. In this paper we conc...
متن کاملDesign Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
Design automation in general, and in particular logic synthesis, can play a key role in enabling the design of application-specific Binarized Neural Networks (BNN). This paper presents the hardware design and synthesis of a purely combinational BNN for ultra-low power near-sensor processing. We leverage the major opportunities raised by BNN models, which consist mostly of logical bit-wise opera...
متن کاملSynthesis of Application-Speci c Memories for Power Optimization in Em bedded Systems
This paper presents a novel approach to memory power optimization for embedded systems based on the exploitation of data locality. Locations with highest access frequency are mapped onto a small, low-power application-speci c memory which is placed close the processor. Although, in principle, a cache may be used to implement such a memory, more e cient solutions may be adopted. We propose an ar...
متن کاملArea and Timing Models for PTL Macrocells
PTL represents a viable alternative to standard CMOS for the implementation of specific units in performance-constrained systems. Unfortunately, this design style has not found wide acceptance in the designers’ community, due to the lack of an established flow for automatic synthesis. In this paper, we present a procedure for constructing area and timing models for PTL macrocells. This is an ke...
متن کامل